– Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs – FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL – Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL-2008 and mixed-language design – Hierarchical team design flow allowing parallel and/or geographically distributed design development – Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx – Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting – Accelerated runtimes with support for up to 4 processors – Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR – Incremental, block-based and bottom-up flows for consistent results from one run to the next
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March 2023
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